Bold People.
Bright Ideas.

Teradar is pioneering a new era in perception with the world’s first automotive terahertz vision sensor, delivering ultra-high resolution imaging in any weather condition. Founded in Boston, Teradar’s solid-state, chip-scale technology unlocks safer, smarter vehicles and opens the door to transformative applications in mobility, defense, and beyond. For more information, visit teradar.com.

Summary

We are seeking a seasoned SoC Expert to work on our custom automotive SoC across the full lifecycle — from architecture modeling, RTL design & verification, synthesis, physical design, tapeout, and post‑silicon validation. This work is in collaboration with our SoC partners, and has to provide technical leadership through its life cycle. This role emphasizes performance, power management innovation and functional safety compliance, ensuring reliable performance for our next‑generation high‑performance sensor systems. With responsibility for guiding post‑silicon debug and corrective tapeouts and driving platform evolution, the ideal candidate will combine deep technical expertise in Arm/RISC CPUs and DSPs with a passion for advancing automotive‑grade semiconductor solutions.

Role Overview

As part of our team, you will play a critical role in ensuring the robustness, efficiency, and scalability of our SoC platform. You will focus on evaluation, optimization, and continuous improvement across the silicon lifecycle, from early modeling through tapeout and silicon bring‑up. 

Key Responsibilities

• Evaluate and optimize the SoC across the full lifecycle: architecture, design, RTL design/verification, synthesis, physical implementation, tapeout, and post‑silicon validation.
• Drive power management strategies, including dynamic voltage/frequency scaling, leakage reduction, and low‑power design techniques.
• Lead post‑silicon debug and corrective tapeouts, ensuring timely resolution of errata and design issues.
• Contribute to platform evolution, enabling next‑generation SoC iterations with enhanced performance, efficiency, and safety features.
• Collaborate with external design houses, foundries, and IP vendors to execute tapeout and silicon bring‑up activities.
• Perform functional safety analysis (ISO 26262) and ensure compliance with automotive industry standards (ASIL, AEC‑Q100).
• Support DFT (Design for Testability) and DFM (Design for Manufacturability) strategies for reliable production.
• Conduct microarchitectural analysis and workload characterization to optimize performance/power trade‑offs.
• Document and communicate findings to cross‑functional teams, enabling informed design decisions.

Qualifications

• 7+ years of experience in SoC design and evaluation, with proven expertise across the full lifecycle (architecture, RTL, synthesis, physical design, tapeout, post‑silicon validation).
• Strong background in Arm/RISC CPU and DSP architectures for high‑performance, low‑power SoCs.
• Experience with functional safety standards (ISO 26262) and certification processes in automotive.
• Hands-on experience with EDA tools (Synopsys, Cadence, Mentor) for simulation, synthesis, and verification.
• Track record of successful tapeouts, including post‑silicon debug and corrective tapeouts.
• Demonstrated contributions to platform evolution in semiconductor programs.
• Excellent communication and collaboration skills, with ability to work across internal and external teams.
• GPU experience is a plus for system‑level performance optimization.

Skills & Competencies

Must Have Skills

• Proven expertise across the SoC lifecycle: architecture modeling, RTL design/verification, synthesis, physical design, tapeout, and post‑silicon validation
• Strong background in Arm/RISC CPUs and DSPs for high‑performance, low‑power SoCs
• Hands‑on experience with EDA tools (Synopsys, Cadence, Mentor) for simulation, synthesis, verification, and sign‑of
• Track record of successful tapeouts, including post‑silicon debug and corrective tapeouts
• Experience with functional safety standards (ISO 26262) and automotive certification processes (ASIL, AEC‑Q100)
• Strong analytical skills for microarchitectural analysis and workload characterization
• Excellent communication and collaboration skills across internal and external teams

Good to Have Skills

• Experience with GPU architectures for parallel compute workloads
• Knowledge of machine learning accelerators or AI‑specific SoC design
• Familiarity with hardware security features (secure boot, crypto accelerators)
• Experience with multi‑die packaging (chiplets, 2.5D/3D IC integration)
• Exposure to automotive networking standards
• Background in sensor signal processing (radar, lidar)
• Prior leadership or mentoring experience in SoC design teams

Responsibilities

• Technical leadership, guiding the design and execution of advanced IC packages for multi-chip RFIC/SoC integration.
• Develop 2.5D packages with UCIe chip-to-chip interconnects and interposer-based solutions.
• Work on single-sided and double-sided RDL designs and on-package RF antenna structures.
• Co-optimize package designs for signal integrity, power integrity, thermal, and mechanical performance in collaboration with RFIC, digital, and system engineers.
• Drive material selection, DFM, and reliability qualification to meet automotive-grade requirements (AEC-Q).
• Perform stress, warpage, and thermal simulations using tools such as ANSYS.
• Maintain and leverage relationships with OSATs, substrate suppliers, and ecosystem partners to accelerate development.
• Create and review electrical performance analysis (signal path length, PDN, crosstalk/noise etc.), mechanical analysis and drawings, stack-ups, and layout constraints.
• Lead failure analysis and root cause investigations for packaging and reliability issues and provide solutions to increase yield.
• Contribute to the packaging roadmap and scalability plan for automotive volume production.

Key Qualifications

• 10+ years of experience in IC packaging design and development, including leadership responsibilities.
• Proven track record with multi-chip packages, digital + RF integration, and automotive applications.
• Deep knowledge of UCIe interconnects, organic substrates, interposers, and advanced packaging architectures.
• Experience with RF antenna integration in package designs.
• Proficient in Flip-Chip, Fan-Out, 2.5D integration, and heterogeneous system-in-package solutions.
• Strong understanding of packaging electrical performance such as signal and power integrity, mechanical stress, thermal management, and reliability analysis.
• Established network with packaging vendors and OSATs.
• M.S. or Ph.D. in Mechanical Engineering, Materials Science, Electrical Engineering, or related field.
• Excellent communication skills and ability to thrive in a fast-paced start-up environment.

Why Join

• Technical oversight, defining packaging solutions for breakthrough ADAS technology.
• Collaborate with a world-class engineering team spanning RFIC, SoC, and system design.
• Be part of a well-funded start-up bringing innovative sensing technology to market.
• Competitive compensation, stock options, and flexible work arrangements.

Location

Hybrid work from one of our offices:

• Bay Area, CA
• Boston, MA

Teradar is seeking a driven and organized RF Systems Engineer with a background in radar systems, RF, or electromagnetics to help bring the world’s first THz phased array imaging system to market.

You’ll work cross-functionally with IC design, antenna/array, signal processing, PCB, packaging, and software teams to support system integration, testing, and characterization of internally developed mmWave ICs. You’ll also play a key role in improving performance, measurement techniques, and scaling system testing.

Most days will involve hands-on debugging and OTA testing of chips and subsystems; others will focus on developing new calibration and test methods and driving implementation logistics. Your work will be central to the technical success and scale-up of the company’s next-gen radar platform.

What You Will Do

• Perform system integration and bring up new versions of the radar system
• Develop and implement new measurement and calibration methods for the radar system
• Develop processes and automation for characterizing a high volume of systems across
• process and temperature corners.
• Solve or participate in solving customer facing system capability improvements
• Manage hardware responsibilities for phased array characterization and analog
• beamforming
• Debug issues with system performance.
• Characterize chipsets over the air using VNAs, spectrum analyzers and frequency extender modules

What You Will Bring 

• Advanced experience with phased array radars
• Experience working at a start-up or high-growth oriented company
• Eager to learn new material, especially related to RF test methods as well as RF system
• design and integration.
• Experience doing over the characterization of antennas and beamforming networks
• System and device level understanding of amplifiers, mixers, phase shifters and other RF components.
• Experience using VNAs, spectrum analyzers and other high frequency lab equipment.
• Strong attention to detail, project/time management, and organizational skills

Location
Boston MA (onsite)

If your jam is low-level programming, high-performance DSPs, and working close to the metal, this one’s for you.

What You Will Do 

• Profile, analyze, and optimize performance, power, and area trade-offs in software designs.
• Develop and optimize embedded software for high-performance multicore DSP platforms.
• Leverage SIMD, VLIW, and fractional arithmetic techniques to deliver efficient signal processing and linear algebra algorithms.
• Work closely with hardware design teams to understand instruction set architectures (ISA) and micro-architectures details, ensuring software takes full advantage of the hardware.
• Integrate DMA strategies to maximize data throughput.
• Build, use, and maintain pre-silicon validation platforms such such as virtual prototypes for early software development and testing.

What You Will Bring

• Strong experience programming for embedded processors or low-level systems.
• Solid understanding of computer architecture and micro-architecture fundamentals.
• Hands-on experience with SIMD and VLIW programming models.
• Knowledge of DMA integration in embedded systems.
• Familiarity with fractional arithmetic in DSP applications.
• Experience working with instruction set architecture (ISA) documentation or development.
• Exposure to virtual prototypes or pre-silicon validation platforms.
• Proficiency in C/C++, Assembly, Intrinsics
• Ability to analyze performance bottlenecks and optimize for PPA.

Bonus Points 

• Individuals who have worked with CEVA DSPs, particularly the SensePro family (SP500/SP1000) and MRD accelerators, will be exceptionally well-suited for this role.
• Familiarity with CEVA’s instruction set, toolchains, and performance optimization techniques will be highly advantageous, especially in the context of high-performance signal processing for sensing applications.

Location
Boston MA (hybrid)